1. Field of the Invention
The present invention relates generally to the field of electronic design automation (EDA), and more specifically to a method for automating optimal placement of macro-blocks in the design of an integrated circuit.
2. Related Art
Integrated circuits (IC) can generally be viewed as containing several macro-blocks (hereafter “macros”) and standard cells. A macro generally refers to a portion of an integrated circuit with a clearly delineated function/utility, and has corresponding input paths and output paths. Examples of such macros include processing blocks and memory blocks. A standard cell generally refers to smaller building blocks which connect the various macros with appropriate transformation (and thus also referred to as glue logic). Examples of standard cells include buffers, latches, multiplexers, etc.
Design of an IC includes several steps such as generating the circuit specifications of the design, partitioning of circuit specifications into various macros, design of individual macros, placement of macros to fit into a desired area, routing of input and output paths between the various macros, post-placement verification of the design, etc., as is well known in the relevant arts.
Thus, one of the steps in the design of an IC is the placement of the various macros. Placement generally refers to the layout (positions) of the various macros/standard cells within a given area (of semi-conductor die). Placement of macros/standard cells may be constrained by design considerations such as maximum allowable die area, power dissipation, length of inter-connected input/output paths (wire-length), etc.
Typically, an IC may contain a large number of macros and standard cells. Placement needs to be optimal at least in the sense that all the design constraints are satisfied and the time and complexity involved are minimized. One typical requirement is that the macros be placed such that there is suitable space (often contiguous and in the center of the die) for placing the standard cells. In one prior approach, placement (layout) of macros is done manually (standard cells are typically placed automatically). However, such an approach of manual macro placement may be time consuming.
Accordingly, what is required is a method of automating optimal placement of macros in the design of an integrated circuit.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.